This invention relates generally to logic circuits and more particularly to clocked circuits.
Computer systems generally operate by performing data transfers between different devices coupled in the system. Often, computer systems include interconnected synchronous devices, that is, devices that use a common signal referred to as a "clock signal" to synchronize timing of circuits in the device. A digital system will have many separate devices some of which may operate with different clock signals that are not synchronous to one another. Moreover, digital systems may also include asynchronous devices i.e., devices that rely upon an occurrence of an asynchronous event. Often, it is necessary to perform data transfers between two synchronous devices each operating with different clock signals (i.e., different clock domains or between a synchronous and an asynchronous device.
An example of such a device is a bus adapter including a first in/first out (FIFO) memory that is loaded or written to from an output device in one clock domain and read by an input device operating under a different clock domain. It is often the case that circuits in either clock domain may need to know the current status of the FIFO in order to operate. For example, one type of information which may be required by circuits in either clock domain is the number of transitions or events that have occurred (e.g., the number of words that have been loaded into the FIFO or read from the FIFO) over a certain interval.